HomeChip Gallery OS-CIM: Output-Stationary SRAM Compute-in-Memory Macro (28nm CMOS), CICC 2025 Sparse Transformer Accelerator (28nm CMOS), ISLPED 2024 SP-IMC: Sparsity-Aware SRAM Compute-in-Memory Macro (28nm CMOS), CICC 2024 Non-Volatile Ferroelectric Capacitive Compute-in-Memory Macro (180nm CMOS), SSCL 2024 PS-IMC: Precision-Scalable SRAM Compute-in-Memory Macro (28nm CMOS), SSCL 2024 3D-ISC: 3D Compatible In-Sensor Computing (65nm CMOS), ASSCC 2023, SSCL 2024 FP-IMC: Floating-Point SRAM Compute-in-Memory Macro (28nm CMOS), ESSCIRC 2023 Vision Sensor with In-Sensor Computing (180nm CMOS), ESSCIRC 2023 RRAM Compute-in-Memory Macro for Genome Sequencing Alignment (65nm CMOS+RRAM), ESSCIRC 2023, JSSC 2024 Physical Unclonable Function with Channel Charge Injection (65nm CMOS), CICC 2023 Delta-Sigma Modulator-based SRAM Compute-in-Memory Macro (65nm CMOS), CICC 2023, SSCL 2023 Sparse AI Training Processor (28nm CMOS), ESSCIRC 2022, JSSC 2023 Fast SRAM Compute-in-Memory Macro (65nm CMOS), ESSCIRC 2022 MACC-SRAM: SRAM In-Memory Computing Macro (28nm CMOS): CICC 2022, JSSC 2024 PIMCA: SRAM In-Memory Computing Accelerator (28nm CMOS), Symp. VLSI 2021, JSSC 2023 CNN Accelerator with Conditional Computing (40nm CMOS), CICC 2020, JSSC 2021 CNN Training Accelerator (65nm CMOS), SSCL 2020 XNOR-RRAM: RRAM In-Memory Computing Macro (90nm CMOS+RRAM), IEEE Micro 2019, TED 2020, SSCL 2020 ECG+PUF Security Engine (65nm CMOS), ASSCC 2019, JSSC 2020 C3SRAM: SRAM In-Memory Computing Macro (65nm CMOS), ESSCIRC 2019, SSCL 2019, JSSC 2020 LSTM Accelerator (65nm CMOS), ESSCIRC 2019, SSCL 2019, JSSC 2020 XNOR-SRAM: In-Memory Computing Macro (65nm CMOS), Symp. VLSI 2018, JSSC 2020 Smart ECG Processor (65nm CMOS), Symp. VLSI 2017, JSSC 2019 Object Detection Accelerator (40nm CMOS), ISCAS 2017, TCAS-I 2019 Photovoltaic power management IC (65nm CMOS), ASSCC 2016, JSSC 2017 ASIC with Threshold Logic Gates (65nm CMOS), CICC 2015 40-phase Switched-Capacitor Voltage Regulator (65nm CMOS), Symp. VLSI 2015, JSSC 2016 Stacked on-chip signaling (45nm CMOS), ISSCC 2013 Neuromorphic chip with on-chip learning (45nm CMOS), CICC 2011 Capacitive on-chip signaling (90nm CMOS), ISSCC 2011 Crosstalk-aware PWM signaling (65nm CMOS), Symp. VLSI 2009, JSSC 2011 Logarithmic ADC (180nm CMOS), Symp. VLSI 2007, JSSC 2009
