2025

• HanGyeol Mun, Jian Meng, Xiaofeng Hu, Yuan Liao, and Jae-sun Seo, “ASAP: A 28nm Transformer Training Accelerator with Alternating Sparsity and Asymmetrical Microscaling Floating-Point Precision,” IEEE Symposium on VLSI Technology and Circuits, June 2025, accepted for publication.
• Jian Meng, Ahmed Hasssan, Li Yang, Deliang Fan, Jinwoo Shin, and Jae-sun Seo, “Closest Neighbors are Harmful for Lightweight Masked Auto-encoders,” IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 2025, accepted for publication.
• Yifan He, Xiaofeng Hu, Hongyang Jia, and Jae-sun Seo, “SRAM and eDRAM-based Compute-in-Memory Designs, Accelerators, and Evaluation Frameworks,” IEEE Solid-State Circuits Magazine (SSC-M), 2025, accepted for publication.
• Han-sok Suh, Jian Meng, and Jae-sun Seo, “Low-Precision Normalization Algorithm and Accelerator for Neural Network Training,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2025, accepted for publication.
• Xiaofeng Hu*, HanGyeol Mun*, Jian Meng, Yuan Liao, Amitesh Sridharan, and Jae-sun Seo, “A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization,” IEEE Custom Integrated Circuits Conference (CICC), April 2025, accepted for publication.
  *Equally-credited authors
• Ahmed Hasssan, Anupreetham Anupreetham, Jian Meng, and Jae-sun Seo, “Quant-NeRF: Efficient End-to-End Quantization of Neural Radiance Fields with Low-Precision 3D Gaussian Representation,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), April 2025, accepted for publication.
• Jason Yik, Korneel Van den Berghe, Douwe den Blanken, Younes Bouhadjar, Maxime Fabre, Paul Hueber, Weijie Ke, Mina A. Khoei, Denis Kleyko, Noah Pacik-Nelson, Alessandro Pierro, Philipp Stratmann, Pao-Sheng Vincent Sun, Guangzhi Tang, Shenqi Wang, Biyan Zhou, Soikat Hasan Ahmed, George Vathakkattil Joseph, Benedetto Leto, Aurora Micheli, Anurag Kumar Mishra, Gregor Lenz, Tao Sun, Zergham Ahmed, Mahmoud Akl, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Petrut Bogdan, Sander Bohte, Sonia Buckley, Gert Cauwenberghs, Elisabetta Chicca, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Tobias Fischer, Jeremy Forest, Vittorio Fra, Steve Furber, P. Michael Furlong, William Gilpin, Aditya Gilra, Hector A. Gonzalez, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Shih-Chii Liu, Yao-Hong Liu, Haoyuan Ma, Rajit Manohar, Josep Maria Margarit-Taulé, Christian Mayr, Konstantinos Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayca Ozcelikkale, Priyadarshini Panda, Jongkil Park, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens J. S. Schaefer, André van Schaik, Johannes Schemmel, Samuel Schmidgall, Catherine Schuman, Jae-sun Seo, Sadique Sheik, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Stewart, Matthew Stewart, Terrence C. Stewart, Jonathan Timcheck, Nergis Tömen, Gianvito Urgese, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Fatima Tuz Zohora, Charlotte Frenkel, and Vijay Janapa Reddi, “The Neurobench Framework for Benchmarking Neuromorphic Computing Algorithms and Systems,” Nature Communications, vol. 16, no. 1545, February 2025.
• Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Umit Y. Ogras, and Yu Cao, “HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025, accepted for publication.
• Yiwei Zhao, Jinhui Chen, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomas Gomez, Jae-sun Seo, Barbara De Salvo, Chiao Liu, Phillip B. Gibbons, Ziyun Li, “H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2025.

2024

• Yuzong Chen, Jian Meng, Jae-sun Seo, and Mohamed Abdelfattah, “BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration,” IEEE/ACM International Symposium on Microarchitecture (MICRO), November 2024.
• Hyung Joon Byun, Udit Gupta, and Jae-sun Seo, “Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 10, pp. 98-106, October 2024. [Special Issue on 3D Logic and Memory for Energy Efficient Computing]
• Jian Meng, Yuecheng Li, Chenghui Li, Syed Shakib Sarwar, Dilin Wang, and Jae-sun Seo, “POCA: Post-training Quantization with Temporal Alignment for Codec Avatars,” European Conference on Computer Vision (ECCV), October 2024.
• Ahmed Hasssan, Jian Meng, Anupreetham, and Jae-sun Seo, “SpQuant-SNN: Ultra-low Precision Membrane Potential with Sparse Activations Unlock the Potential of On-device Spiking Neural Networks Applications,” Frontiers of Neuroscience, Section Neuromorphic Computing, vol. 18, September 2024.
• Ahmed Hasssan, Jian Meng, Anupreetham and Jae-sun Seo, “IM-SNN: Memory-Efficient Spiking Neural Network with Low-Precision Membrane Potentials and Weights,” ACM International Conference on Neuromorphic Systems (ICONS), August 2024. [Best Paper Candidate]
• Hyung Joon Byun, Udit Gupta, and Jae-sun Seo, “3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2024.
• Yuan Liao, Jian Meng and Jae-sun Seo, “A 28nm Scalable and Flexible Accelerator for Sparse Transformer Models,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2024. [Best Paper Candidate]
• Fan Zhang, Amitesh Sridharan, Wangxin He, Injune Yeo, Maximilian Liehr, Wei Zhang, Nathaniel Cady, Yu Cao, Jae-sun Seo, and Deliang Fan, “A 65nm RRAM Compute-in-Memory Macro for Genome Processing,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 7, pp. 2093-2104, July 2024. [Invited for Special Issue on 2023 ESSCIRC]
• Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, and Yu Cao, “SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024.
• Ahmed Hasssan, Jian Meng, and Jae-sun Seo, “Spiking Neural Network with Learnable Threshold for Event-Based Classification and Object Detection,” IEEE International Joint Conference on Neural Networks (IJCNN), July 2024.
• Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, and Mingoo Seok, “MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 6, pp. 1938-1949, June 2024.
• Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hasssan, Shixing Yu, Han-sok Suh, Xiaofeng Hu, and Jae-sun Seo, “Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design,” Conference on Machine Learning and Systems (MLSys), May 2024. [Github Repo]
• Amitesh Sridharan, Fan Zhang, Jae-sun Seo, and Deliang Fan, “SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads,” IEEE Custom Integrated Circuits Conference (CICC), April 2024.
• H. Ekin Sumbul, Jae-sun Seo, Daniel Morris, and Edith Beigne, “A Fully-Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator with SoC-Level Benchmarking for AR/VR Applications,” IEEE Micro, vol. 44, no. 2, pp. 61-70, March-April 2024.
• Gopikrishnan Raveendran Nair, Pragnya S. Nalla, Gokul Krishnan, Anupreetham, Jonghyun Oh, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Mingoo Seok, Jae-sun Seo, and Yu Cao, “3D In-Sensor Computing for Real-time DVS Data Compression: 65nm Hardware-Algorithm Co-design,” IEEE Solid-State Circuits Letters (SSC-L), vol. 7, pp. 119-122, March 2024. [Invited for Special Issue on 2023 ASSCC]
• Amitesh Sridharan, Jyotishman Saikia, Anupreetham, Fan Zhang, Jae-sun Seo, and Deliang Fan, “PS-IMC: A 2385.7 TOPS/W/b Precision Scalable In-Memory Computing Macro with Bit-Parallel Inputs and Decomposable Weights for DNNs,” IEEE Solid-State Circuits Letters (SSC-L), vol. 7, pp. 102-105, March 2024.
• Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, and Jae-sun Seo, “A Dynamic Power-only Compute-In-Memory Macro with Power-of-Two Nonlinear SAR ADC for Non-volatile Ferroelectric Capacitive Crossbar Array,” IEEE Solid-State Circuits Letters (SSC-L), vol. 7, pp. 70-73, February 2024.
• Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, and Yu Cao, “Transformer-based Selective Super-Resolution for Efficient Image Refinement,” AAAI Conference on Artificial Intelligence, February 2024.
• Zhenyu Wang, Jingbo Sun, Alper Goksoy, Sumit Kumar Mandal, Yaotian Liu, Jae-sun Seo, Chaitali Chakrabarti, Umit Y. Ogras, Vidya Chhabria, Jeff Zhang, and Yu Cao, “Exploiting 2.5D/3D Heterogeneous Integration for AI Computing,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2024. [Invited]
• Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, and Yu Cao, “Patch-based Selection and Refinement for Early Object Detection,” Winter Conference on Applications of Computer Vision (WACV), January 2024.
• Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, and Jae-sun Seo, “High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 17, no. 1, pp. 1–20, January 2024.
• Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga, “Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC),” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 1, pp. 4-7, January 2024.

2023

• Jian Meng, Li Yang, Kyungmin Lee, Jinwoo Shin, Deliang Fan, and Jae-sun Seo, “Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training,” Advances in Neural Information Processing Systems (NeurIPS), December 2023.
• Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, and Yu Cao, “3D-ISC: a 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression,” IEEE Asian Solid-State Circuits Conference (ASSCC), November 2023.
• Zhenyu Wang, Jingbo Sun, Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Chaitali Chakrabarti, Umit Y. Ogras, Vidya Chhabria, and Yu Cao, “Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling,” IEEE International Conference on ASIC (ASICON), October 2023.
• Vasundhara Damodaran, Ziyu Liu, Jian Meng, Jae-sun Seo, and Arindam Sanyal, “SRAM In-Memory Computing Macro With Delta-Sigma Modulator Based Variable-Resolution Activation,” IEEE Solid-State Circuits Letters, vol. 6, pp. 293-296, October 2023. [Invited for Special Issue on 2023 CICC]
• Vasundhara Damodaran, Ziyu Liu, Jian Meng, Jae-sun Seo, and Arindam Sanyal, “A Delta-Sigma Based SRAM Compute-in-Memory Macro for Human Activity Recognition,” IEEE Biomedical Circuits and Systems Conference (BioCAS), October 2023.
• Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras and Yu Cao, “In-Memory Computing for AI Accelerators: Challenges and Solutions,” Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer Link, October 2023. [Book Chapter]
• Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas Venkataramanaiah, Deliang Fan, and Jae-sun Seo, “FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2023.
• Dong-Woo Jee, Seong-Min Ko, Kishore Kasichainular, Injune Yeo, Yu Cao, and Jae-sun Seo, “A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2023.
• Fan Zhang, Wangxin He, Injune Yeo, Maximilian Liehr, Nathaniel Cady, Yu Cao, Jae-sun Seo, and Deliang Fan, “A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2023.
• Shreyas K. Venkataramanaiah, Jian Meng, Han-sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, and Jae-sun Seo, “A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 7, pp. 1885-1897, July 2023. [Invited for Special Issue on 2022 ESSCIRC]
• Jae-sun Seo, “Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators,” ACM/IEEE Design Automation Conference (DAC), July 2023.
• Min-Kyu Song, Ji-Hoon Kang, Xinyuan Zhang, Wonjae Ji, Alon Ascoli, Ioannis Messaris, Ahmet Samil Demirkol, Bowei Dong, Samarth Aggarwal, Weier Wan, Seok-Man Hong, Suma George Cardwell, Irem Boybat, Jae-sun Seo, Jang-Sik Lee, Mario Lanza, Hanwool Yeon, Murat Onen, Ju Li, Bilge Yildiz, Jesús A. del Alamo, Seyoung Kim, Shinhyun Choi, Gianluca Milano, Carlo Ricciardi, Lambert Alff, Yang Chai, Zhongrui Wang, Harish Bhaskaran, Mark C. Hersam, Dmitri Strukov, H.-S. Philip Wong, Ilia Valov, Bin Gao, Huaqiang Wu, Ronald Tetzlaff, Abu Sebastian, Wei Lu, Leon Chua, J. Joshua Yang, and Jeehwan Kim, “Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems,” ACS Nano, vol. 17, no. 13, pp. 11994-12039, June 2023.
• Sahra Afshari, Sritharini Radhakrishnan, Jing Xie, Mirembe Musisi-Nkambwe, Jian Meng, Wangxin He, Jae-sun Seo, and Ivan Sanchez Esqueda, “Dot-Product Computation and Logistic Regression with 2D Hexagonal-Boron Nitride (h-BN) Memristor Arrays,” 2D Materials, vol. 10, no. 3, pp. 035031, June 2023.
• Gokul Krishnan, Sumit K. Mandal, A. Alper Goksoy, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras and Yu Cao, “End-to-End Benchmarking of Chiplet-Based In-Memory Computing,” Neuromorphic Computing, IntechOpen, June 2023. [Book Chapter]
• Han-sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, and Jae-sun Seo, “Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 16, no. 2, pp. 1-25, May 2023.
• Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, and Mingoo Seok, “PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 5, pp. 1436-1449, May 2023.
• Tianyi Zhang, Kishore Kasichainula, Dong-Woo Jee, Injune Yeo, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, and Yu Cao, “Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2023.
• Injune Yeo, Dong-Woo Jee, and Jae-sun Seo, “A 92F²/bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation,” IEEE Custom Integrated Circuits Conference, April 2023.
• Vasundhara Damodaran, Ziyu Liu, Jae-sun Seo, and Arindam Sanyal, “A 138-TOPS/W Delta-Sigma Modulator-Based Variable-Resolution Activation In-Memory Computing Macro,” IEEE Custom Integrated Circuits Conference, April 2023.
• Zhenyu Wang, Pragnya Sudershan Nalla, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, and Yu Cao, “Digital-Assisted Analog In-Memory Computing with RRAM Devices,” International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), April 2023.
• Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, and Jae-sun Seo, “PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration,” IEEE Design, Automation & Test in Europe (DATE), April 2023.
• Gopikrishnan Raveendran Nair*, Han-sok Suh*, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, and Yu Cao, “FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix,” IEEE Design, Automation & Test in Europe (DATE), April 2023.
  *Equally-credited authors

2022

• Li Yang*, Jian Meng*, Jae-sun Seo, and Deliang Fan, “Get More at Once: Alternating Sparse Training with Gradient Correction,” Advances in Neural Information Processing Systems (NeurIPS), December 2022.
  *Equally-credited authors
• Zhenyu Wang, Gopikrishnan Raveendran Nair, Gokul Krishnan, Sumit K. Mandal, Ninoo Cherian, Jae-sun Seo, Chaitali Chakrabarti, Umit Y. Ogras, and Yu Cao, “AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-memory Acceleration,” IEEE International Electron Devices Meeting (IEDM), December 2022.
• Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao, and Deliang Fan, “XMA²: A Crossbar-Aware Multi-Task Adaption Framework via 2-Tier Masks,” Frontiers in Electronics (Section on Integrated Circuits and VLSI), vol. 3, December 2022.
• Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, and Yu Cao, “Hybrid RRAM/SRAM In-Memory Computing for Robust DNN Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4241-4252, November 2022.
• Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Umit Ogras, and Yu Cao, “Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture,” IEEE International Conference On Computer Aided Design (ICCAD), November 2022.
• Ahmed Hasssan, Jian Meng, Yu Cao, and Jae-sun Seo, “Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder,” IEEE Asilomar Conference on Signals, Systems, and Computers, November 2022.
• Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Han-Sok Suh, Shihui Yin, Gokul Krishnan, Frank Liu, Jae-sun Seo, and Yu Cao, “Efficient Continual Learning at the Edge with Progressive Segmented Training,” Neuromorphic Computing and Engineering, vol. 2, no. 4, October 2022.
• Gokul Krishnan, Zhenyu Wang, Li Yang, Injune Yeo, Jian Meng, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, and Yu Cao, “IMC Architecture for Robust DNN Acceleration,” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 2022. [Invited]
• Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, and Yu Cao, “Hybrid RRAM/SRAM In-Memory Computing for Robust DNN Acceleration,” International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Embedded Systems Week (ESWEEK), October 2022.
• Shreyas K. Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, and Jae-sun Seo, “A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2022.
• Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae-sun Seo, and Deliang Fan, “A 1.23-GHz 16-Kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2022.
• Sai Kiran Cherupally, Jian Meng, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, and Jae-sun Seo, “Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection,” IEEE Design & Test, vol. 39, no. 4, pp. 71-80, August 2022.
• Injune Yeo and Jae-sun Seo, “Resistive Memories Stack Up,” Nature Electronics, vol. 5, no. 7, pp. 414-415, July 2022. [News & Views Article]
• Xu Han, Matthew Spear, Jae-sun Seo, Donald Wilson, Trace Wallace, Oliver Forman, Jose Solano, Marek Turowski, Matthew Marinella, Hugh J. Barnaby, “Total Ionizing Dose Effects in FDSOI SRAM-Based XNOR IMC Synaptic Array,” IEEE Nuclear & Space Radiation Effects Conference (NSREC), July 2022.
• Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao, and Deliang Fan, “XMA: A Crossbar-aware Multi-task Adaption Framework via Shift-based Mask Learning Method,” ACM/IEEE Design Automation Conference (DAC), July 2022.
• Jae-sun Seo, Jyotishman Saikia, Jian Meng, Wangxin He, Han-sok Suh, Anupreetham, Yuan Liao, Ahmed Hasssan, and Injune Yeo, “Digital Versus Analog Artificial Intelligence Accelerators: Advances, Trends, and Emerging Designs,” IEEE Solid-State Circuits Magazine (SSC-M), vol. 14, no. 3, pp. 65-79, Summer 2022.
• Jian Meng, Li Yang, Jinwoo Shin, Deliang Fan, and Jae-sun Seo, “Contrastive Dual Gating: Learning Sparse Features With Contrastive Learning,” IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 2022.
• Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, and Mingoo Seok, “A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks,” IEEE Custom Integrated Circuits Conference (CICC), April 2022.
• Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, and Yu Cao, “Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 2, pp. 1-22, April 2022.
• Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, and Jae-sun Seo, “Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference,” IEEE International Reliability Physics Symposium (IRPS), March 2022. [Invited]
• Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao and Deliang Fan, “XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning,” IEEE Design, Automation & Test in Europe (DATE), March 2022. [Best IP (Interactive Presentations) Paper Award]
• Jian Meng, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, and Jae-sun Seo, “Temperature-Resilient RRAM-based In-Memory Computing for DNN Inference,” IEEE Micro, vol. 42, no. 1, pp. 89-98, January/February 2022. [Special Issue on Processing in Memory]
• Sai Kiran Cherupally, Jian Meng, Adnan Rakin, Shihui Yin, Injune Yeo, Shimeng Yu, Deliang Fan, and Jae-sun Seo, “Improving the Accuracy and Robustness of RRAM-based In-Memory Computing Against RRAM Hardware Noise and Adversarial Attacks,” Semiconductor Science and Technology, vol. 37, no. 3, January 2022.  [Special Issue on Neuromorphic Devices and Applications]
• Fan Zhang, Li Yang, Jian Meng, Yu Cao, Jae-sun Seo, and Deliang Fan, “XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2022.

2021

• Arnab Neelim Mazumder, Jian Meng, Hasib-Al Rashid, Utteja Kallakuri, Xin Zhang, Jae-sun Seo, and Tinoosh Mohsenin, “A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 11, no. 4, pp. 532-547, December 2021.
• Han-sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, and Jae-sun Seo, “Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA,” IEEE International Conference on Field-Programmable Technology (FPT), December 2021.
• Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, and Jae-sun Seo, “Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robustness Improvement of DNN Hardware Against Adversarial Input and Weight Attacks,” ACM/IEEE Design Automation Conference (DAC), December 2021.
• Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Umit Ogras, and Yu Cao, “SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks,” ACM Transactions on Embedded Computing Systems, vol. 20, no. 5s, October 2021.
• Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun. Seo, Umit Ogras and Yu Cao, “System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration,” IEEE International Conference on ASIC (ASICON), October 2021.
• Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, and Jae-sun Seo, “End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), September 2021. [Best Paper Candidate]
• Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul Whatmough, and Jae-sun Seo, “FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), September 2021.
• Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, and Jae-sun Seo, “PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference,” IEEE Symposium on VLSI Circuits, June 2021.
• Xu Han, Aymeric Privat, Keith E. Holbert, Jae-sun Seo, Shimeng Yu, and Hugh J. Barnaby, “Total Ionizing Dose Effect on Multi-state HfOx-based RRAM Synaptic Array,” IEEE Transactions on Nuclear Science (TNS), vol. 68, no. 5, pp. 756-761, May 2021.
• Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, and Jae-sun Seo, “Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks,” IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 68, no. 5, pp. 1576-1580, May 2021. [Invited for Special Issue on 2021 ISCAS]
• Vinay Joshi, Wangxin He, Jae-sun Seo, and Bipin Rajendran, “Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
• Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, and Jae-sun Seo, “Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
• Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, and Jae-sun Seo, “Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing,” IEEE International Reliability Physics Symposium (IRPS), March 2021. [Best Student Paper Candidate]
• Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, and Shimeng Yu, “Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine,” IEEE International Reliability Physics Symposium (IRPS), March 2021.
• Minkyu Kim and Jae-sun Seo, “Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 3, pp. 803-813, March 2021. [Invited for Special Issue on 2020 CICC]
• Jae-sun Seo and Shimeng Yu, “Neuro-Inspired Computing and Neuromorphic Processors for Biomedical Circuits and Systems,” Chapter in Selected Topics in Biomedical Circuits and Systems, River Publishers Series in Circuits and Systems, February 2021.
• Jyotishman Saikia, Shihui Yin, Bo Zhang, Jian Meng, Mingoo Seok and Jae-sun Seo, “Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design,” IEEE Design, Automation & Test in Europe (DATE), February 2021.

2020

• Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, and Yu Cao, “Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs,” IEEE Design & Test, vol. 37, no. 6, pp. 79-87, December 2020.
• Xu Han, Aymeric Privat, Keith E. Holbert, Jae-sun Seo, Shimeng Yu, and Hugh Barnaby, “Total Ionizing Dose Effect on Multi-state HfOx-based RRAM Synaptic Array,” IEEE Nuclear & Space Radiation Effects Conference (NSREC), December 2020.
• Yandong Luo, Xu Han, Zhilu Ye, Hugh Barnaby, Jae-sun Seo, and Shimeng Yu, “Array Level Programming of 3-bit Per Cell Resistive Memory and Its Application for Deep Neural Network Inference,” IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4621-4625, November 2020. [Special Section on 2020 ESSDERC]
• Shreyas Venkataramanaiah, Han-sok Suh, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, and Jae-sun Seo, “FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory“, IEEE International Conference On Computer Aided Design (ICCAD), November 2020.
• Wonbo Shim, Jae-sun Seo, and Shimeng Yu, “Two-Step Write-Verify Scheme and Impact of the Read Noise in Multilevel RRAM based Inference Engine,” Semiconductor Science and Technology, vol. 35, no. 11, October 2020.
• Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 10, pp. 3680-3690, October 2020. [Invited for Special Issue on 2019 ASSCC]
• Shihui Yin, Xiaoyu Sun, Shimeng Yu, and Jae-sun Seo, “High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS,” IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4185-4192, October 2020.
• Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, and Jae-sun Seo, “Deep Neural Network Training Accelerator Designs in ASIC and FPGA,” IEEE International SoC Conference (ISOCC), October 2020. [Invited]
• Deepak Kadetotad, Jian Meng, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity,” INTERSPEECH, October 2020.
• Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-sun Seo, Yu Cao, and Umit Y. Ogras, “A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 10, no. 3, pp. 362-375, September 2020.
• Usama Awais and Jae-sun Seo, “Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2020.
• Wangxin He, Shihui Yin, Yulhwa Kim, Xiaoyu Sun, Jae-Joon Kim, Shimeng Yu, and Jae-sun Seo, “2-Bit-per-Cell RRAM based In-Memory Computing for Area-/Energy-Efficient Deep Learning,” IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 194-197, July 2020. [Special Section on 2020 ESSCIRC]
• Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 7, pp. 1888-1897, July 2020. [Invited for Special Issue on 2019 ESSCIRC]
• Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 7, pp. 1877-1887, July 2020. [Invited for Special Issue on 2019 ESSCIRC]
• Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, and Yu Cao, “Online Knowledge Acquisition with Selective Inherited Model,” IEEE International Joint Conference on Neural Networks (IJCNN), July 2020. [Best Student Paper Finalist]
• Wonbo Shim, Yandong Luo, Jae-sun Seo, and Shimeng Yu, “Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM based Deep Learning Inference Engine,” IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2318-2323, June 2020.
• Shihui Yin, Zhewei Jiang, Jae-sun Seo, and Mingoo Seok, “XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 6, pp. 1733-1743, June 2020.
• Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Jae-sun Seo, and Shimeng Yu, “A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.
• Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Performance Modeling for CNN Inference Accelerators on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 843-856, April 2020.
• Wonbo Shim, Yandong Luo, Jae-sun Seo, and Shimeng Yu, “Impact of Read Disturb on Multi-level RRAM based Inference Engine: Experiments and Model Prediction,” IEEE International Reliability Physics Symposium (IRPS), March 2020.
• Shruti Kulkarni, Shihui Yin, Jae-sun Seo, and Bipin Rajendran, “An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays,” IEEE Design, Automation & Test in Europe (DATE), March 2020.
• Minkyu Kim and Jae-sun Seo, “Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access,” IEEE Custom Integrated Circuits Conference (CICC), March 2020.
• Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Automatic Compilation of Diverse CNNs onto High-Performance FPGA Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 2, pp. 424-437, February 2020.
• Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Gaurav Srivastava, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “ECG Authentication Hardware Design with Low-Power Signal Processing and Neural Network Optimization with Low Precision and Structured Compression,“ IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 14, no. 2, pp. 198-208, February 2020. [Special Section on AI-Based Biomedical Circuits and Systems]
• Shihui Yin and Jae-sun Seo, “A 2.6 TOPS/W 16-bit Fixed-Point Convolutional Neural Network Learning Processor in 65nm CMOS,” IEEE Solid-State Circuits Letters (SSC-L), vol. 3, no. 1, pp. 13-16, January 2020.
• Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, and Jae-sun Seo, “Vesti: Ultra-Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 1, pp. 48-61, January 2020. [IEEE TVLSI Best Paper Award] <

2019

• Shihui Yin, Yandong Luo, Yulhwa Kim, Wangxin He, Xu Han, Xiaoyu Sun, Hugh Barnaby, Jae-Joon Kim, Shimeng Yu, and Jae-sun Seo, “Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning,” IEEE Micro, vol. 39, no. 6, pp. 54-63, November/December 2019.
• Shruti Kulkarni, Deepak Kadetotad, Shihui Yin, Jae-sun Seo, and Bipin Rajendran, “Neuromorphic Hardware Accelerator for SNN Inference Based on STT-Ram Crossbar Arrays,” IEEE International Conference on Electronics, Circuits and Systems, November 2019.
• Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation,” IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2019.
• Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, and Jae-sun Seo, “Vesti: Ultra-Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks,” IEEE Asilomar Conference on Signals, Systems, and Computers, November 2019. [Invited]
• Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, and Shimeng Yu, “Inference Engine Benchmarking Across Technological Platforms from CMOS to RRAM,” The International Symposium on Memory Systems (MEMSYS), October 2019.
• Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: In-Memory Computing SRAM Macro Based on Capacitive-Coupling Computing,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 9, pp. 131-134, September 2019. [Invited for Special Issue on 2019 ESSCIRC]
• Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “A 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 9, pp. 119-122, September 2019. [Invited for Special Issue on 2019 ESSCIRC]
• Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: In-Memory Computing SRAM Macro Based on Capacitive-Coupling Computing,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2019. [IEEEXplore link]
• Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “A 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2019.
• Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, and Jae-sun Seo, “Automatic Compiler Based FPGA Accelerator for CNN Training,“ International Conference on Field-Programmable Logic and Applications (FPL), September 2019.
• Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, and Jae-sun Seo, “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 8, pp. 2316-2326, August 2019.
• Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, and Jae-sun Seo, “K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019.
• Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, and Jae-sun Seo, “A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS,” IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 66, no. 10, pp. 3843-3853, June 2019.
• Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Chisung Bae, Sang Joon Kim, and Jae-Sun Seo, “ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.
• Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “XNOR-SRAM: In-Bitcell Computing SRAM Macro based on the Resistive Computing Mechanism,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2019. [Invited]
• Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2019.
• Mingoo Seok, Minhao Yang, Zhewei Jiang, Aurel. A. Lazar, Jae-sun Seo, “Cases for Analog-Mixed-Signal Computing Integrated-Circuits for Deep Neural Networks,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April 2019. [Invited]
• Paul Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas Venkataramanaiah, Jae-sun Seo, and Matthew Mattina, “FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning,” Conference on Systems and Machine Learning (SysML), April 2019.

2018

• Chetan S. Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun M. Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, and Ralph Etienne-Cummings, “Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain,” Frontiers of Neuroscience, vol. 12, pp. 891, December 2018.
• Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, and Sung-Kyu Lim, “Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 14, no. 4, November 2018.
• Yufei Ma, Tu Zheng, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2018.
• Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, and Chaitali Chakrabarti, “A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks,” IEEE International Workshop on Signal Processing Systems (SiPS), October 2018.
• Robert D’Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao, Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, and Sameer Sonkusale, “Process Scalability of Pulse Based Circuits for Analog Image Convolution,” IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 65, no. 9, pp. 2929-2938, September 2018.
• Shruti R. Kulkarni, Deepak Kadetotad, Jae-sun Seo, and Bipin Rajendran, “Well-Posed Verilog-A Compact Model for Phase Change Memory,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2018.
• Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 7, pp. 1354-1367, July 2018.
• Yufei Ma, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “ALAMO: FPGA Acceleration of Deep Learning Algorithms with a Modularized RTL Compiler,” Integration, the VLSI Journal, vol. 62, pp. 14-23, June 2018.
• Zhewei Jiang, Shihui Yin, Mingoo Seok, and Jae-sun Seo, “XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks,” IEEE Symposium on VLSI Circuits, June 2018.
• Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Sarma Vrudhula, Junseok Chae, Yu Cao, and Visar Berisha, “Towards a Wearable Cough Detector Based on Neural Networks,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), April 2018.
• Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Li, Jae-sun Seo, and Chang Song, “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 8, no. 1, pp. 6-27, March 2018.
• Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, and Shimeng Yu, “XNOR-RRAM: A Scalable and Parallel Synaptic Architecture for Binary Neural Networks,” Design, Automation & Test in Europe (DATE), March 2018.
• Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, and Shimeng Yu, “Fully Parallel RRAM Synaptic Array for Implementing Binary Neural Network with (+1, -1) Weights and (+1, 0) Neurons,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018.

2017

• Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, and Yu Cao, “Improving Efficiency in Sparse Learning with the Feedforward Inhibitory Motif,” Neurocomputing, vol. 267, no. C, pp. 141-151, December 2017.
• Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, and Yu Cao, “Random Sparse Adaptation for Accurate Inference with Inaccurate Multi-Level RRAM Arrays,” IEEE International Electron Devices Meeting (IEDM), December 2017.
• Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, and Mingoo Seok, ‘‘Triple-Mode, Hybrid-Storage Energy Harvesting Power Management Unit: Achieving High Efficiency against Harvesting and Load Variabilities,’’ IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 10, pp. 2550-2562, October 2017. [Invited for Special Issue on 2016 ASSCC]
• Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, and Jae-sun Seo, “Minimizing Area and Energy of Deep Learning Hardware Design Using Binarization and Structured Compression,” Asilomar Conference on Signals, Systems, and Computers, October 2017. [Invited]
• Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, and Jae-sun Seo, “Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations,” IEEE Biomedical Circuits and Systems Conference (BioCAS), October 2017.
• Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), September 2017.
• Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo and Sung Kyu Lim, “Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2017.
• Shihui Yin, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “Designing ECG-based Physical Unclonable Function for Security of Wearable Devices,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), July 2017.
• Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, and Jae-sun Seo, “Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs,” International Work-Conference on Artificial Neural Networks, pp. 271-282, June 2017.
• Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, and Jae-sun Seo, “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring,” IEEE Symposium on VLSI Circuits, June 2017. [Selected as one of the technical highlights] [Press Kit]
• Yufei Ma, Minkyu Kim, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “End-to-End Scalable FPGA Accelerator for Deep Residual Networks,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
• Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, and Jae-sun Seo, “A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
• Deepak Kadetotad, Pai-Yu Chen, Yu Cao, Shimeng Yu, and Jae-sun Seo, “Peripheral Circuit Design Considerations of Neuro-inspired Architectures,” Chapter in Neuro-inspired Computing Using Resistive Synaptic Devices, pp. 167-182, Springer International Publishing, April 2017.
• Xiaoyang Mi, Hesam Fathi Moghadam, and Jae-sun Seo, “Flying and Decoupling Capacitance Optimization for Area-Constrained On-Chip Switched-Capacitor Voltage Regulators,” Design, Automation & Test in Europe (DATE), March 2017.
• Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), February 2017.
• Shihui Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti and Jae-sun Seo, “Low-Power Neuromorphic Speech Recognition Engine with Coarse-Grain Sparsity,” Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017. [Invited]

2016

• Mohit Shah, Sairam Arunachalam, Jingcheng Wang, David Blaauw, Dennis Sylvester, Hun-Seok Kim, Jae-sun Seo, and Chaitali Chakrabarti, “A Fixed-Point Neural Network Architecture For Speech Applications on Resource Constrained Hardware,” Journal of Signal Processing Systems, doi:10.1007/s11265-016-1202-x, 2016.
• Dawei Zhou, Jingrui He, Yu Cao, and Jae-sun Seo, “Bi-level Rare Temporal Pattern Detection,” IEEE International Conference on Data Mining (ICDM), December 2016.
• Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, and Mingoo Seok, “Triple-Mode Photovoltaic Power Management: Achieving High Efficiency against Harvesting and Load Variability,” IEEE Asian Solid-State Circuits Conference (ASSCC), November 2016.
• Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, and Jae-sun Seo, “Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016.
• Pai-Yu Chen, Jae-sun Seo, Yu Cao, and Shimeng Yu, “Compact Oscillation Neuron Exploiting Metal-Insulator-Transition for Neuromorphic Computing,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016.
• Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, and Sarma Vrudhula, “Reducing Power, Leakage and Area of Standard Cell ASICs Using Threshold Logic Flipflops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2873-2886, September 2016.
• Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, and Sarma Vrudhula, “Scalable and Modularized RTL Compilation of Convolutional Neural Networks onto FPGA,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), September 2016.
• Ming Tu, Visar Berisha, Yu Cao, and Jae-sun Seo, “Reducing the Model Order of Deep Neural Networks Using Information Theory,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2016. [Invited]
• Luis Ceze, Jennifer Hasler, Konstantin K. Likharev, Jae-sun Seo, Tim Sherwood, Dmitri Strukov, Yuan Xie, and Shimeng Yu, “Nanoelectronic Neurocomputing: Status and Prospects,” Device Research Conference (DRC), June 2016. [Invited]
• Soochan Lee, Dhinakaran Pandiyan, Jae-sun Seo, Patrick E. Phelan, and Carole-Jean Wu, “Thermoelectric-based Sustainable Self-Cooling for Fine-Grained Processor Hot Spots,” IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2016.
• Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma Vrudhula, Jae-sun Seo, and Yu Cao, “High-Performance Face Detection with CPU-FPGA Acceleration,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.
• Zihan Xu, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, and Yu Cao, “Hardware-Efficient Learning with Feedforward Inhibition,” IEEE International Nanoelectronics Conference (INEC), May 2016. [Invited]
• Suyoung Bang, Jae-sun Seo, Leland Chang, David Blaauw, and Dennis Sylvester, “A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 919-929, April 2016. [Invited for Special Issue on 2015 Symp. on VLSI Circuits]
• Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, and Yu Cao, “Ranking the Parameters of Deep Neural Networks Using the Fisher Information,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 2647-2651, March 2016.
• Naveen Suda, Ganesh Dasika, Vikas Chandra, Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-sun Seo, and Yu Cao, “Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 16-25, February 2016.

2015

• Jae-sun Seo, Binbin Lin, Minkyu Kim, Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Sarma Vrudhula, Shimeng Yu, Jieping Ye, Yu Cao, “On-Chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices,” IEEE Transactions on Nanotechnology (TNANO), vol. 14, no. 6, pp. 969-979, November 2015.
• Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma Vrudhula, Jae-sun Seo, Yu Cao, and Shimeng Yu, “Mitigating Effects of Non-Ideal Synaptic Device Characteristics for On-Chip Learning,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 194-199, November 2015.
• Ligang Gao, I-Ting Wang, Pai-Yu Chen, Sarma Vrudhula, Jae-sun Seo, Yu Cao, Tuo-Hung Hou, and Shimeng Yu, “Fully Parallel Write/Read in Resistive Synaptic Array for Accelerating On-Chip Learning,” Nanotechnology, vol. 26, 455204, October 2015.
• Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, and Sarma Vrudhula, “Energy-Efficient Reconstruction of Compressively Sensed Bioelectrical Signals with Stochastic Computing Circuits,” IEEE International Conference on Computer Design (ICCD), pp. 443-446, October 2015.
• Jae-sun Seo and Mingoo Seok, “Digital CMOS Neuromorphic Processor Design Featuring Unsupervised Online Learning,” IFIP/IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 49-51, October 2015. [Invited]
• Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, and Sarma Vrudhula, “Dynamic and Leakage Power Reduction of ASICs Using Configurable Threshold Logic Gates,“ IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, September 2015.
• Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, and Mingoo Seok, “A Neuromorphic Neural Spike Clustering Processor for Deep-Brain Sensing and Stimulation Systems,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 91-97, July 2015.
• Xiaoyang Mi, Debashis Mandal, Visvesh Sathe, Bertan Bakkaloglu, and Jae-sun Seo, “Fully-Integrated Switched-Capacitor Voltage Regulator with On-Chip Current-Sensing and Workload Optimization in 32nm SOI CMOS,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 140-145, July 2015.
• Visvesh Sathe and Jae-sun Seo, “Analysis and Optimization of CMOS Switched-Capacitor Voltage Converters,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 327-334, July 2015.
• Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma Vrudhula, Shimeng Yu, Yu Cao, and Jae-sun Seo, “Parallel Architecture with Resistive Crosspoint Array for Dictionary Learning Acceleration,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 194-204, June 2015.
• Suyoung Bang, Jae-sun Seo, Inhee Lee, Seokhyeon Jeong, Nathaniel Pinckney, David Blaauw, Dennis Sylvester, and Leland Chang, “A Fully-Integrated 40-Phase Flying-Capacitance-Dithered Switched-Capacitor Voltage Regulator with 6mV Output Ripple,” IEEE Symposium on VLSI Circuits, pp. C336-C337, June 2015.
• Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma Vrudhula, Jae-sun Seo, Yu Cao, and Shimeng Yu, “Technology-Design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip,” Design, Automation & Test in Europe (DATE), pp. 854-859, March 2015.

2014

• Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Deepak Kadetotad, Jieping Ye, Sarma Vrudhula, Shimeng Yu, Jae-Sun Seo, and Yu Cao, “Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity,” International Conference on Biologically Inspired Cognitive Architectures (BICA), pp. 126-133, November 2014.
• Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma Vrudhula, Shimeng Yu, Yu Cao, and Jae-sun Seo, “Neurophysics-Inspired Parallel Architecture of Resistive Crosspoint Array for Dictionary Learning,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 536-539, October 2014.

2013

• Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert Montoye, Leland Chang, José A. Tierno, and Daniel Friedman, “A 0.1pJ/b 5-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45-nm CMOS SOI,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 400-401, February 2013.
• Bipin Rajendran, Yong Liu, Jae-sun Seo, Kailash Gopalakrishnan, Leland Chang, Daniel Friedman, and Mark Ritter, “Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, January 2013.

2011

• Jae-sun Seo, David Blaauw, and Dennis Sylvester, “Crosstalk-Aware PWM-Based On-Chip Links with Self-Calibration in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), September 2011, vol. 46, no. 9, pp. 2041-2052, September 2011.
• Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin Parker, Steven K. Esser, Robert Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, and Daniel Friedman, “A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, September 2011.
• Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, and Ram Krishnamurthy, “A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 264-273, February 2011.

2010

• Jae-sun Seo, Ron Ho, Jon Lexau, Michael Dayringer, Dennis Sylvester, and David Blaauw, “High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 182-183, February 2010.
• David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, and David Blaauw, “In Situ Delay Slack Monitor for High-Performance Processors using an All-Digital, Self-Calibrating 5ps Resolution Time-to-Digital Converter,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 188-189, February 2010.

2009

• Jongwoo Lee, Joshua Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, and Michael Flynn, “A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 10, pp. 2755-2765, October 2009.
• Jae-sun Seo, Dennis Sylvester, and David Blaauw, “Crosstalk-Aware PWM-Based On-Chip Global Signaling in 65nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 88-89, June 2009.

2008

• Jae-sun Seo, Igor Markov, Dennis Sylvester, and David Blaauw, “On the Decreasing Significance of Large Standard Cells in Technology Mapping,” IEEE International Conference on Computer-Aided Design (ICCAD), pp. 116-121, November 2008.
• Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, and David Blaauw, “Robust Ultra-Low Voltage ROM Design,” IEEE Custom Integrated Circuit Conference (CICC), pp. 423-426, September 2008.
• Prashant Singh, Jae-sun Seo, David Blaauw, and Dennis Sylvester, “Self-timed Regenerators for High-speed and Low-power Global Interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 673-677, June 2008.
• Himanshu Kaul, Jae-sun Seo, Mark Anders, Dennis Sylvester, and Ram Krishnamurthy, “A Robust Alternate Repeater Technique for High Performance Busses in the Multi-Core Era,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 372-375, May 2008.

2007

• Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, and Ram Krishnamurthy, “A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.68-73, August 2007.
• Jongwoo Lee, Sunghyun Park, Joshua Kang, Jae-sun Seo, Jens Anders, and Michael Flynn, “A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC,” IEEE Symposium on VLSI Circuits, pp.194-195, June 2007.
• Jae-sun Seo, Prashant Singh, David Blaauw, and Dennis Sylvester, “Self-Timed Regenerators for High-speed and Low-power Interconnects,” ACM/IEEE International Symposium on Quality Electronic Design (ISQED), pp.621-626, March 2007. [Best Paper Award Nominee]